SCANPSC100F集成電路（IC）的控制器規(guī)格書PDF中文資料

General Description

The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus. It is useful in improving scan throughput when applying serial vectors to system test circuitry and reduces the software overhead that is associated with applying serial patterns with a parallel processor.

Features

■ Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture

■ Supported by Fairchild’s SCAN Ease (Embedded Application Software Enabler) Software

■ Uses generic, asynchronous processor interface; compatible with a wide range of processors and PCLK frequencies

■ Directly supports up to two 1149.1 scan chains

■ 16-bit Serial Signature Compaction (SSC) at the Test Data In (TDI) port

■ Automatically produces pseudo-random patterns at the Test Data Out (TDO) port

■ Fabricated on FACT? 1.5 μm CMOS process

■ Supports 1149.1 test clock (TCK) frequencies up to 25 MHz

■ TTL-compatible inputs; full-swing CMOS outputs with 24 mA source/sink capability