SH7285中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

This LSI is a single-chip RISC microprocessor that integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration. The CPU in this LSI has a RISC-type (Reduced Instruction Set Computer) instruction set and use a superscalar architecture and a Harvard architecture, which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low-cost, high-performance, and high functioning systems, even for applications that were previously impossible with microprocessors, such as realtime control, which demands high speeds. In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as a large-capacity ROM, a ROM cache, a RAM, a direct memory access controller (DMAC), a data transfer controller (DTC), multi-function timer pulse units 2 (MTU2 and MTU2S), a serial communication interface with FIFO (SCIF), a serial communication interface (SCI), a synchronous serial communication interface (SSU), an A/D converter, a D/A converter, an interrupt controller (INTC), I/O ports, I2C bus interface 3 (IIC3), a universal serial bus (USB), and a controller area network (RCAN-ET).