SI5518中文資料思佳訊數(shù)據(jù)手冊PDF規(guī)格書

Applications:

? LTE-A and 5G Remote Radio Units (RRU)

? JESD204B/C clock generation

? IEEE1588 slave clocks (T-TSC), Telecom Boundary Clocks (T-BC)

? IEEE1588 Assisted Partial Timing support clocks (T-BC-A, T-TSC-A), Partial Timing

Support (T-BC-P, T-TSC-P)

? IEEE 1588 Grandmaster clocks (T-GM)

? Remote Access Networks (RAN), picocells, small cells

? Remote Radio Heads (RRH), wireless repeaters, mobile fronthaul and backhaul

1. Feature List

? RFPLL (RF DSPLL)

? Supports JESD204B/C Subclass 0, 1, and 2 Clocking

? Ultra-low Phase Noise (example at 491.52 MHz carrier):

? –164 dBc/Hz noise floor

? –145 dBc/Hz at 800 kHz offset

? Ultra-low jitter performance:

? <50 fs typ XO (12 kHz–20 MHz at 491.52 MHz)

? <45 fs typ VCXO (12 kHz–20 MHz at 491.52 MHz)

? Selectable jitter attenuation bandwidth: 10 Hz to 4 kHz, 30 Hz to 4 kHz Dual Reference JA

? DSPLL A, DSPLL B

? Independent network synchronization DSPLLs

? Supports ITU-T G.8273.2 (T-TSC, T-BC) and ITU-T G.8273.4 (T-BC-P, T-BC-A, T-TSC-P, T-TSC-A)

? Programmable loop bandwidth: 1 mHz to 4 kHz

? Automatic Free-Run, Holdover, and Locked modes

? Hitless input clock switching: automatic or manual with < 150 ps phase transient

? PPSPLL

? Instant lock for 1PPS/PP2S

? Programmable loop bandwidth 1 mHz to 25 mHz

? Programmable phase slope limiting (PSL) and phase pull-in rate (PPI)

? 18 Programmable Clock Outputs:

? JESD204B/C DCLK or SYSREF. Up to nine DCLK/SYSREF pairs

? Integer Q dividers: PP2S/1PPS to 3.2 GHz

? JESD204B/C SYSREF pulser mode

? Multisynth Fractional Dividers: PP2S/1PPS to 650 MHz

? Output-to-Output Static Delay: ±10 ns

? Output-output skew: ±50 ps

? LVDS, S-LVDS, AC coupled LVPECL, LVCMOS, Slew Rate Limited (SRL) LVCMOS, HCSL, CML

? Utilizes fifth-generation DSPLL? and MultiSynth? technologies

? Zero Delay Mode for all PLLs

? 4/6 clock inputs:

? Differential: 8 kHz to 1 GHz

? CMOS: 1 PPS, PP2S, 8 kHz to 250 MHz

? Status monitoring (LOS, OOF, PHMON, FLOL and PLOL)

? Automatically generates free-running clocks at power up

? Automatically locks to a valid clock input

? Automatic holdover mode

? Core voltage: 3.3 V, 1.8 V

? Output driver supply voltages (VDDO): 3.3 V, 2.5 V, 1.8 V

? Serial Interface: I2C or SPI (3 or 4-wire)

? ClockBuilder Pro? software tool simplifies device configuration

? Package: 72-Lead QFN, 10x10 mm

? Extended temperature range:

? –40 to +95 °C ambient

? –40 to +105 °C board

? Pb-free, RoHS compliant