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SL4029BDW中文資料SLS數(shù)據(jù)手冊PDF規(guī)格書

SL4029BDW
廠商型號

SL4029BDW

功能描述

Presettable Up/Down Counter

文件大小

84.88 Kbytes

頁面數(shù)量

8

生產(chǎn)廠商 System Logic Semiconductor
企業(yè)簡稱

SLS

中文名稱

System Logic Semiconductor官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-5-24 23:01:00

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SL4029BDW規(guī)格書詳情

Presettable Up/Down Counter

High-Voltage Silicon-Gate CMOS

The SL4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consists of a single CLOCK, CARRY IN,(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs.

Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times.

? Operating Voltage Range: 3.0 to 18 V

? Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C

? Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

產(chǎn)品屬性

  • 型號:

    SL4029BDW

  • 制造商:

    SLS

  • 制造商全稱:

    System Logic Semiconductor

  • 功能描述:

    Presettable Up/Down Counter

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