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SL74HCT373中文資料SLS數(shù)據(jù)手冊(cè)PDF規(guī)格書
| 廠商型號(hào) |
SL74HCT373 |
| 功能描述 | Octal 3-State Noninverting Transparent Latch(High-Performance Silicon-Gate CMOS) |
| 文件大小 |
52.61 Kbytes |
| 頁面數(shù)量 |
5 頁 |
| 生產(chǎn)廠商 | System Logic Semiconductor |
| 企業(yè)簡稱 |
SLS |
| 中文名稱 | System Logic Semiconductor官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-5-24 20:00:00 |
| 人工找貨 | SL74HCT373價(jià)格和庫存，歡迎聯(lián)系客服免費(fèi)人工找貨 |
SL74HCT373規(guī)格書詳情
Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS
The SL74HCT373 may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs.
The SL74HCT373 is identical in pinout to the LS/ALS373.
The eight latches of the SL74HCT373 are transparent D-type latches. While the Latch Enable is high the Q outputs follow the Data Inputs. When Latch Enable is taken low, data meeting the setup and hold times becomes latched.
The Output Enable does not affect the state of the latch, but when Output Enable is high, all outputs are forced to the high-impedance state. Thus, data may be latched even when the outputs are not enabled.
? TTL/NMOS-Compatible Input Levels
? Outputs Directly Interface to CMOS, NMOS, and TTL
? Operating Voltage Range: 4.5 to 5.5 V
? Low Input Current: 1.0 μA
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990000 |
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10 |
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SLKOR/薩科微 |
25+ |
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