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SN54SC6T07MPWTSEP中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

SN54SC6T07MPWTSEP
廠商型號

SN54SC6T07MPWTSEP

功能描述

SN54SC6T07-SEP Radiation Tolerant, Hex Open-Drain Buffers with Integrated Translation

絲印標(biāo)識

SC07SEP

封裝外殼

TSSOP

文件大小

1.0382 Mbytes

頁面數(shù)量

23

生產(chǎn)廠商 Texas Instruments
企業(yè)簡稱

TI1德州儀器

中文名稱

德州儀器官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-2-16 16:00:00

SN54SC6T07MPWTSEP規(guī)格書詳情

1 Features

? Vendor item drawing available, VID V62/24617

? Total ionizing dose characterized at 30 krad (Si)

– Total ionizing dose radiation lot acceptance

testing (TID RLAT) for every wafer lot to 30

krad (Si)

? Single-event effects (SEE) characterized:

– Single event latch-up (SEL) immune to linear

energy transfer (LET) = 43 MeV-cm2 /mg

– Single event transient (SET) characterized to

43 MeV-cm2 /mg

? Wide operating range of 1.2V to 5.5V

? Single-supply translating gates at

5/3.3/2.5/1.8/1.2V VCC

– TTL compatible inputs:

? Up translation:

– 1.8-V – Inputs from 1.2V

– 2.5V – Inputs from 1.8V

– 3.3V – Inputs from 1.8V, 2.5V

– 5.0V – Inputs from 2.5V, 3.3V

? Down translation:

– 1.2V – Inputs from 1.8V, 2.5V, 3.3V, 5.0V

– 1.8-V – Inputs from 2.5V, 3.3V, 5.0V

– 2.5V – Inputs from 3.3V, 5.0V

– 3.3V – Inputs from 5.0V

? 5.5V tolerant input pins

? Output drive up to 25mA AT 5V

? Latch-up performance exceeds 250mA per

JESD 17

? Space enhanced plastic (SEP)

– Controlled baseline

– Gold bondwire

– NiPdAu lead finish

– One assembly and test site

– One fabrication site

– Military (–55°C to 125°C) temperature range

– Extended product life cycle

– Product traceability

– Meets NASAs ASTM E595 outgassing

specification

2 Applications

? Enable or disable a digital signal

? Controlling an indicator LED

? Translation between communication modules and

system controllers

3 Description

The SN54SC6T07-SEP device contains six

independent buffers with open-drain outputs and

extended voltage operation to allow for level

translation. Each buffer performs the Boolean function

Y = A in positive logic. The output level is referenced

to the supply voltage (VCC) and supports 1.2V, 1.8-V,

2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to

support up translation for lower voltage CMOS inputs

(for example 1.2V input to 1.8V output or 1.8V input

to 3.3V output). Additionally, the 5V tolerant input pins

enable down translation (for example 3.3V to 2.5V

output).

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