首頁>SN74LV2T74-EP>規(guī)格書詳情

SN74LV2T74-EP中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

SN74LV2T74-EP
廠商型號

SN74LV2T74-EP

功能描述

SN74LV2T74-EP Enhanced Product, Dual D-Type Flip-Flop With Integrated Translation

文件大小

997.64 Kbytes

頁面數(shù)量

21

生產廠商 Texas Instruments
企業(yè)簡稱

TI德州儀器

中文名稱

美國德州儀器公司官網

原廠標識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-3-29 23:00:00

人工找貨

SN74LV2T74-EP價格和庫存,歡迎聯(lián)系客服免費人工找貨

SN74LV2T74-EP規(guī)格書詳情

1 Features

? Wide operating range of 1.8 V to 5.5 V

? Single-supply voltage translator (refer to LVxT

Enhanced Input Voltage):

– Up translation:

? 1.2 V to 1.8 V

? 1.5 V to 2.5 V

? 1.8 V to 3.3 V

? 3.3 V to 5.0 V

– Down translation:

? 5.0 V, 3.3 V, 2.5 V to 1.8 V

? 5.0 V, 3.3 V to 2.5 V

? 5.0 V to 3.3 V

? 5.5-V tolerant input pins

? Supports standard pinouts

? Up to 150 Mbps with 5-V or 3.3-V VCC

? Latch-up performance exceeds 250 mA

per JESD 17

? Supports defense, aerospace, and medical

applications:

– Controlled baseline

– One assembly and test site

– One fabrication site

– Extended product life cycle

– Product traceability

2 Applications

? Convert a momentary switch to a toggle switch

? Hold a signal during controller reset

? Input slow edge-rate signals

? Operate in noisy environments

? Divide a clock signal by two

3 Description

The SN74LV2T74-EP contains two independent Dtype

positive-edge-triggered flip-flops. A low level at

the preset (PRE) input sets the output high. A low

level at the clear (CLR) input resets the output low.

Preset and clear functions are asynchronous and not

dependent on the levels of the other inputs. When

PRE and CLR are inactive (high), data at the data

(D) input meeting the setup time requirements is

transferred to the outputs (Q, Q) on the positive-going

edge of the clock (CLK) pulse. Clock triggering occurs

at a voltage level and is not directly related to the

rise time of the input clock (CLK) signal. Following

the hold-time interval, data at the data (D) input can

be changed without affecting the levels at the outputs

(Q, Q). The output level is referenced to the supply

voltage (VCC) and supports 1.8-V, 2.5-V, 3.3-V, and

5-V CMOS levels.

The input is designed with a lower threshold circuit to

support up translation for lower voltage CMOS inputs

(for example, 1.2 V input to 1.8 V output or 1.8 V input

to 3.3 V output). In addition, the 5-V tolerant input pins

enable down translation (for example, 3.3 V to 2.5 V

output).

供應商 型號 品牌 批號 封裝 庫存 備注 價格
TI(德州儀器)
23+
SOP14
7350
現(xiàn)貨供應,當天可交貨!免費送樣,原廠技術支持!!!
詢價
TI
2020+
SOIC-14
80000
只做自己庫存,全新原裝進口正品假一賠百,可開13%增
詢價
TI
22+
14SOIC
9000
原廠渠道,現(xiàn)貨配單
詢價
TI/德州儀器
22+
TSSOP
20000
原裝現(xiàn)貨,實單支持
詢價
24+
SSOP
500
本站現(xiàn)庫存
詢價
TexasInstruments
18+
ICQUAD2-INPUTORGATE14-SO
6800
公司原裝現(xiàn)貨/歡迎來電咨詢!
詢價
TI
21+
原廠原裝
13880
公司只售原裝,支持實單
詢價
1000
原裝正品
詢價
TI/德州儀器
2447
TSSOP14
100500
一級代理專營品牌!原裝正品,優(yōu)勢現(xiàn)貨,長期排單到貨
詢價
TI
23+
N/A
8000
只做原裝現(xiàn)貨
詢價