ST72F324BJ集成電路（IC）的微控制器規(guī)格書PDF中文資料

ST72F324BJ屬于集成電路（IC）的微控制器。由意法半導(dǎo)體集團制造生產(chǎn)的ST72F324BJ微控制器微控制器產(chǎn)品是相對復(fù)雜的用戶可編程數(shù)字邏輯器件。這些產(chǎn)品與視為微控制器的器件密切相關(guān)，兩者之間的區(qū)別主要體現(xiàn)在制造商選擇的用詞。不過按照傳統(tǒng)，微控制器集成了工作存儲器，也更可能包含混合信號外設(shè)，并且往往與更簡單的軟件范例結(jié)合使用，旨在重復(fù)執(zhí)行一系列預(yù)定義的任務(wù)。

INTRODUCTION

The ST72324K and ST72324J devices are members of the ST7 microcontroller family. They can be grouped as follows:

– The 32-pin ST72324K devices are designed for mid-range applications

– The 42/44-pin ST72324J devices target the same range of applications requiring more than 24 I/O ports.

All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set and are available with FLASH or ROM program memory.

■ Memories

– 8 to 32K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In-Application Programming and InCircuit Programming for HDFlash devices

– 384 to 1K bytes RAM

– HDFlash endurance: 100 cycles, data retention: 20 years at 55°C

■ Clock, Reset And Supply Management

– Enhanced low voltage supervisor (LVD) for main supply with 3 programmable reset thresholds and auxiliary voltage detector (AVD) with interrupt capability

– Clock sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock

– PLL for 2x frequency multiplication

– Four Power Saving Modes: Halt, Active-Halt, Wait and Slow

■ Interrupt Management

– Nested interrupt controller

– 10 interrupt vectors plus TRAP and RESET

– 9/6 external interrupt lines (on 4 vectors)

■ Up to 32 I/O Ports

– 32/24 multifunctional bidirectional I/O lines

– 22/17 alternate function lines

– 12/10 high sink outputs

■ 4 Timers

– Main Clock Controller with: Real time base, Beep and Clock-out capabilities

– Configurable watchdog timer

– 16-bit Timer A with: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes

– 16-bit Timer B with: 2 input captures, 2 output compares, PWM and pulse generator modes

■ 2 Communication Interfaces

– SPI synchronous serial interface

– SCI asynchronous serial interface (LIN compatible)

■ 1 Analog Peripheral

– 10-bit ADC with up to 12 input pins

■ Instruction Set

– 8-bit Data Manipulation

– 63 Basic Instructions

– 17 main Addressing Modes

– 8 x 8 Unsigned Multiply Instruction

■ Development Tools

– Full hardware/software development package

– In-Circuit Testing capability