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STGAP2HD中文資料意法半導體數據手冊PDF規(guī)格書

STGAP2HD
廠商型號

STGAP2HD

功能描述

Galvanically isolated 4 A dual gate driver

文件大小

803.17 Kbytes

頁面數量

24

生產廠商 STMicroelectronics
企業(yè)簡稱

STMICROELECTRONICS意法半導體

中文名稱

意法半導體集團官網

原廠標識
數據手冊

下載地址一下載地址二到原廠下載

更新時間

2025-3-29 10:28:00

人工找貨

STGAP2HD價格和庫存,歡迎聯(lián)系客服免費人工找貨

STGAP2HD規(guī)格書詳情

Features

? High voltage rail up to 1200 V

? Driver current capability: 4 A sink/source @ 25 °C

? dV/dt transient immunity ±100 V/ns

? Overall input-output propagation delay: 75 ns

? Separate sink and source option for easy gate driving configuration

? 4 A Miller CLAMP

? UVLO function

? Configurable interlocking function

? Dedicated SD and BRAKE pins

? Gate driving voltage up to 26 V

? 3.3 V, 5 V TTL/CMOS inputs with hysteresis

? Temperature shutdown protection

? Standby function

? 6 kV galvanic isolation

? Wide Body SO-36W

? UL 1577 recognized

Application

? Motor driver for industrial drives, factory automation, home appliances and fans

? 600/1200 V inverters

? Battery chargers

? Induction heating

? Welding

? UPS

? Power supply units

? DC-DC converters

? Power Factor Correction

Description

The STGAP2HD is a dual gate driver which provides galvanic isolation between

each gate driving channel and the low voltage control and interface circuitry. The

gate driver is characterized by 4 A current capability and rail-to-rail outputs, making

it suitable for mid and high power applications such as power conversion and

industrial motor driver inverters. The separated output pins allow to independently

optimize turn-on and turn-off by using dedicated gate resistors, while the Miller

CLAMP function allows avoiding gate spikes during fast commutations in half-bridge

topologies. The device integrates protection functions: dedicated SD and BRAKE

pins are available, UVLO and thermal shutdown are included to easily design high

reliability systems. In half-bridge topologies the interlocking function prevents outputs

from being high at the same time, avoiding shoot-through conditions in case of wrong

logic input commands. The interlocking function can be disabled by a dedicated

configuration pin, so to allow independent and parallel operation of the two channels.

The input to output propagation delay results are contained within 75 ns, providing

high PWM control accuracy. A standby mode is available in order to reduce idle

power consumption.

供應商 型號 品牌 批號 封裝 庫存 備注 價格
ST
24+
SOP
15000
原裝原標原盒 給價就出 全網最低
詢價
ST/意法
22+
SOP
9000
原裝正品,支持實單!
詢價
ST
5
只做正品
詢價
24+
N/A
70000
一級代理-主營優(yōu)勢-實惠價格-不悔選擇
詢價
ST/意法
2324+
SOIC-8
78920
二十余載金牌老企,研究所優(yōu)秀合供單位,您的原廠窗口
詢價
ST/意法
21+
原廠COC隨貨
500000
原裝正品
詢價
STMicroelectronics
23+
TO-18
12800
原裝正品代理商最優(yōu)惠價格,現貨或訂貨
詢價
ST
22+
30000
原裝現貨,可追溯原廠渠道
詢價
STN
2324+
21000
原裝正品,超低價出售
詢價
ST/意法
22+
SOP
15000
原裝正品
詢價