SY100EP196VTGTR中文資料麥瑞半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The SY100EP196V is a programmable delay line, varying the time a logic signal takes to traverse from IN to Q. This delay can vary from about 2.2ns to about 12.2ns. The input can be PECL, LVPECL, NECL, or LVNECL.

The delay varies in discrete steps based on a control word presented to SY100EP196V. The 10-bit width of this latched control register allows for delay increments of approximately 10ps. In addition, delay may be varied continuously in about a 30ps range by setting the voltage at the FTUNE pin.

An eleventh control bit allows the cascading of multiple SY100EP196V devices, for a wider delay range. Each additional SY100EP196V effectively doubles the delay range available.

FEATURES

■ Pin-for-pin, plug-in compatible to the ON Semiconductor MC100EP196

■ Maximum frequency > 2.5GHz

■ Programmable range: 2.2ns to 12.2ns

■ 10ps increments

■ 30ps fine tuning range

■ PECL mode operating range: VCC = 3.0V to 5.5V with VEE = 0V

■ NECL mode operating range: VCC = 0V with VEE = –3.0V to –5.5V

■ Open input default state

■ Safety clamp on inputs

■ A logic high on the /EN pin will force Q to logic low

■ D[0:10] can accept either ECL, CMOS, or TTL inputs

■ VBB output reference voltage

■ Available in a 32-pin TQFP package