TC511001Z-12中文資料東芝數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The TC511001P/J/Z is the new generation dynamic

RAM organized 1,048,576 words by 1 bit. The

TC511001P/J/Z utilizes TOSHIBA's CMOS Silicon gate

process technology as well as advanced circuit techniques

to provide wide operating margins, both internally and

to the system user. Multiplexed address inputs permit the

TC511001P/J/Z to be packaged in a standard 18 pin

plastic DIP, 26/20 pin plastic SOJ and 20/19 pin plastic

ZIP. The package size provides high system bit densities

and is compatible with widely available automated testing

and insertion equipment. System oriented features

include single power supply of 5V ± 10 tolerance,

direct interfacing capability with high performance logic

families such as Schottky TTL. The special feature of

TC511001P/J/Z is nibble mode, allowing the user to

serially access 4 bits of data at a high data rate. Test

Mode function is implemented from Revision C.

FEATURES

1,048,576 word by 1 bit organization

Fast access time and cycle time

TRAC

TAA

tCAC

tRc

INCAC

RAS Access Time

Column Address Access

Time

INC

CAS Access Time

Cycle Time

Nibble Mode Access

Time

Nibble Mode Cycle

Time

TC511001P/J/Z-85-10-12

85ns

100ns

45ns 50ns

30ns

35ns

165ns

190ns

20ns

20ns

120ns

60ns

40ns

220ns

25ns

40ns 40ns 50ns

Single power supply of 5V ± 10 with a built-in VBB

generator

Low Power:

385mW MAX. Operating (TC511001P/J/Z-85)

330mW MAX. Operating (TC511001P/J/Z-10)

275mW MAX. Operating (TC511001P/J/Z-12)

5.5mW MAX. Standby

Output unlatched at cycle end allows two-dimensional

clip selection

Common I/O capability using EARLY WRITE

operation

Read-Modify-Write, CAS before RAS refresh, RAS-

only refresh, Hidden refresh, Nibble Mode and Test

Mode capability

? All inputs and output TTL compatible

? 512 refresh cycles/8ms

● Packing

Plastic DIP TC511001P

Plastic SOJ: TC511001J

Plastic ZIP: TC511001Z