TC518128BFTL中文資料東芝數(shù)據(jù)手冊PDF規(guī)格書

Description

The TC518128B-V is a 1M bit high speed CMOS pseudo static RAM organized as 131,072 words by 8 bits. The TC518128B-V

utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed and low power

storage. The TC518128B-V operates from a single power supply of 2.7-5.5V. Refreshing is supported by a refresh (RFSH) input

which enables two types of refreshing - auto refresh and self refresh. The TC518128B-V features a static RAM-like interface with a

write cycle in which the input data is written into the memory cell at the rising edge of R/W thus simplifying the microprocessor

interface.

The TC518128B-V is pin-compatible with the 1M bit CMOS static RAM JEDEC standard and is available in a 32-pin, 0.6 inch

width plastic DIP, a small outline plastic flat package, and a 32-pin thin small outline plastic package (forward type).

Features

?

Organization:

? Low voltage operation

? Data retention supply voltage:

? Fast access time

tCEA CE Access Time

toEA OE Access Time

tRc Cycle Time

Power Dissipation

Self Refresh Current

5.5V

3.0V

131,072 words x 8 bits

2.7V-5.5V

2.7V-5.5V

TC518128B-V Family

-80

80ns

30ns

130ns

330mW

50μA

25μA

-70

70ns

25ns

115ns

385mW

? Auto refresh is supported by an internal refresh address

counter

? Self refresh is supported by an internal timer

? Inputs and outputs TTL compatible

? Refresh: 512 refresh cycles/8ms

? Auto refresh power down feature

? Pin compatible: 1M SRAM (JEDEC)

Package

-10

100ns

40ns

160ns

275mW

- TC518128BPL: DIP32-P-600

TC518128BFL: SOP32-P-450

TC518128BFWL: SOP32-P-525

TC518128BFTL: TSOP32-P-0820