TC551632J-25中文資料東芝數(shù)據(jù)手冊PDF規(guī)格書

Description

The TC551632J is a 524,288 bit high speed CMOS static random access memory organized as 32,768 words by 16 bits and

operated from a single 5V supply. Toshiba's advanced CMOS technology and circuit design enable high speed operation.

The TC551632J features low power dissipation when the device is deselected using chip enable (CE), and has an output

enable input (OE) for fast memory access. Byte access is supported by upper and lower byte controls.

The TC551632J is suitable for use in high speed applications such as cache memory and high speed storage. All inputs and out-

puts are TTL compatible.

The TC551632J is available in a 400mil width, 40-pin SOJ suitable for high density surface assembly.

Features

? Fast access time

- TC551632J-20

- TC551632J-25

- TC551632J-35

Low power dissipation

Cycle Time

Operation (max.)

20ns (max.)

25ns (max.)

35ns (max.)

25 35 100

130

20

220 200 170

Standby:

1mA (max.)

Single 5V power supply: 5V±10

Fully static operation

Inputs and outputs TTL compatible

? Output buffer control: OE

Data byte controls:

LB, UB

? Package:

SOJ40-P-400

ns

mA