TC58NVG1S3BFT00中文資料東芝數(shù)據(jù)手冊(cè)PDF規(guī)格書

2 GBIT (256M × 8 BIT/128M × 16 BIT) CMOS NAND E2PROM

DESCRIPTION

The TC58NVG1SxB is a single 3.3 V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes/(1024 + 32) words × 64 pages × 2048 blocks. The device has a 2112-byte/1056-word static register which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages).

FEATURES

? Organization

TC58NVG1S3B TC58NVG1S8B

Memory cell array 2112 × 128K × 8 1056 × 128K × 16

Register 2112 × 8 1056 × 16

Page size 2112 bytes 1056 words

Block size (128K + 4K) bytes (64K + 2K) words

? Modes

Read, Reset, Auto Page Program, Auto Block Erase， Status Read

? Mode control

Serial input/output

Command control

? Number of valid blocks

Max 2048 blocks

Min 2008 blocks

? Power supply

VCC = 2.7 V to 3.6 V

? Program/Erase Cycles

100000 Cycles (With ECC)

? Access time

Cell array to register 25 μs max

Serial Read Cycle 50 ns min

? Program/Erase time

Auto Page Program 200 μs/page typ.

Auto Block Erase 1.5 ms/block typ.

? Operating current

Read (50 ns cycle) 10 mA typ.

Program (avg.) 10 mA typ.

Erase (avg.) 10 mA typ.

Standby 50 μA max

? Package

TC58NVG1S3BFT00 TSOP I 48-P-1220-0.50

TC58NVG1S8BFT00 TSOP I 48-P-1220-0.50

(Weight: 0.53 g typ.)