TCP631-ED中文資料TEWS數(shù)據(jù)手冊PDF規(guī)格書

Application Information

The TCP631 is a standard 3U 32 bit CompactPCI

module providing a user configurable FPGA with

1,500,000 system gates. All local signals from the

PCI controller are routed to the FPGA.

The TCP631 offers 64 I/O lines to the front I/O and

64 I/O lines to the rear I/O. For flexible front I/O

solutions the TCP631 provides a PIM Module slot,

allowing active and passive signal conditioning. An

option offers additionally 64 I/O lines via the J2

connector. All I/O lines are directly connected to the

FPGA-pins, which maintains the flexibility of the

Select I/O technology of the Spartan III FPGA. All

I/O lines provide external ESD-protection devices. In

addition the FPGA is connected to two banks of 128

Mbytes, 16 bit wide DDR2 SDRAM.

The FPGA is configured by a parallel flash. The

flash device is in-system programmable via driver

software over the PCI bus. An in-circuit debugging

option is available via an optionally mountable JTAG

header for readback and real-time debugging of the

FPGA design (using Xilinx “ChipScope”).

A programmable clock generator supplies up to four

different clock frequencies between 5 kHz and

200 MHz which are available at the FPGA, in

addition one clock source is used as the local clock

signal for the PCI controller. The clock generator

settings are stored in an EEPROM and can be

changed by the driver software.

The configuration EEPROM of the PCI controller can

also be modified by the driver software, to adapt

address spaces etc.

User applications for the TCP631 can be developed

using the design software ISE WebPACK which can

be downloaded free of charge from www.xilinx.com.