TIP360中文資料TEWS數(shù)據(jù)手冊PDF規(guī)格書

Application Information

The TIP360 is an IndustryPack? compatible module with a serial communication I/O interface using the Motorola MC68360 Quad Integrated Communication Processor running at 25 MHz.

The MC68360 contains a CPU32 core processor, a micro coded RISC communication processor, 14 serial DMA channels, two independent DMAs, 4 general purpose timers, an interrupt controller, 4 independent full-duplex serial communication controllers (SCCs), two Serial Management Controllers (SMCs) and 2.5 kbytes Dual-Port of internal RAM.

The TIP360 provides TTL level interface for all 4 SCC’s of the MC68360 at the IP I/O connector. A variety of physical layer standards, such as RS232, RS422, RS485, ISDN or IEEE802.3/Ethernet can be supported by the use of custom transition modules.

Internal microcode in the MC68360 supports a variety of protocols, such as BISYNC, HDLC, SDLC, UART, DDCMP, AppleTalk, Signaling System #7, Profibus, ATM, V.14, X.21, ISDN and totally transparent modes.

The TIP360 provides additional to the internal RAM 256 kbyte of SRAM, 256 kbyte of Flash memory, 2 Mbytes of “DRAM” (realized with SRAM and on board logic to maintain existing 68360 board configuration) as dual-port memory. Select SRAM or Flash memory as boot memory by switching a control register. The code is downloaded to the SRAM or Flash memory by the IP host CPU prior to removing the MC68360 reset signal by writing to a control register. Once the MC68360 reset signal is removed, the MC68360 starts fetching code from boot memory.

The SRAM, Flash memory, DRAM, the MC68360 registers and the MC68360 on-chip RAM are accessible by the MC68360 and the IP host CPU by arbitration. The local bus arbitration is transparent to the IP host CPU.

Both the IP host CPU and the MC68360 are capable of generating interrupts to each other.