TS68302DESC01QXC中文資料愛特梅爾數(shù)據(jù)手冊(cè)PDF規(guī)格書

Description

The IMP is a very large-scale integration (VLSI) device incorporating the main building blocks needed for the design of a wide variety of controllers. The device is especially suitable to applications in the communications industry. The IMP is the first device to offer the benefits of a closely coupled, industry-standard, TS68000/TS68008 microprocessor core and a flexible communications architecture.

Features

? TS68000/TS68008 Microprocessor Core Supporting a 16- or 8-bit TS68000 Family

? System Integration Block Including:

– Independent Direct Memory Access (IDMA) Controller

– Interrupt Controller with Two Modes of Operation

– Parallel Input/output (I/O) Ports, some with Interrupt Capability

– On-chip Usable 1152 bytes of Dual-port Random-access Memory (RAM)

– Three Timers, including a Watchdog Timer

– Four Programmable Chip-select Lines with Wait-state Logic

– Programmable Address Mapping of Dual-port RAM and IMP Registers

– On-chip Clock Generator with an Output Clock Signal

– System Control:

System Control Register

Bus Arbitration Logic with Low Interrupt Latency Support

Hardware Watchdog for Monitoring Bus Activity

Low Power (Standby) Modes

Disable CPU Logic (TS68000)

Freeze Control for Debugging Selected On-chip Peripherals

DRAM Refresh Controller

? Communications Processor Including:

– Main Controller (RISC Processor)

– Three Full-duplex Serial Communication Controllers (SCCs)

– Six Serial Direct Memory Access (SDMA) Channels Dedicated to the Three SCCs

– Flexible Physical Interface Accessible by SCCs for Interchip Digital Link (IDL)

General Circuit Interface (GCI, see note), Pulse Code Modulation (PCM), and

Nonmultiplexed Serial Interface (NMSI) Operation

– Serial Communication Port (SCP) for Synchronous Communication, Clock Rate up to 4.096 MHz

– Serial Management Controllers (SMCs) for IDL and GCI Channels

? Frequency of Operation: 16.67 MHz

? Power Supply: 5 VDC ± 10