TXV0108QWRGYRQ1中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

1 Features

? Supports up to 500-Mbps for 1.65 V to 3.6 V

? AEC-Q100 qualified for automotive applications

? Meets RGMII 2.0 timing specifications:

– < 750 ps rise and fall time

– < ± 5 duty cycle distortion

– < ± 400 ps channel to channel skew

– Up to 250Mbps/channel

? Integrated 10 Ω damping output resistor to

minimize signal reflections

? High drive strength (up to 12 mA at 3.6 V)

? Fully configurable symmetric dual-rail design

? Optimal signal integrity performance with 390ps

peak-to-peak jitter for 1.8 V to 3.3 V

? Features VCC isolation and VCC disconnect

? Ioff supports partial-power-down mode operation

? Latch-up performance exceeds 100 mA per JESD

78, Class II

? ESD protection exceeds JESD 22:

– 2000-V Human-Body Model

– 1000-V Charged-Device Model

? Low power consumption:

– 10-μA maximum (25°C)

– 20-μA maximum (–40°C to 125°C)

? Operating temperature from –40°C to +125°C

? Pin compatible with SN74AVC8T245 (VQFN)

? Available in wettable flank VQFN (RGY) Package

2 Applications

? Medium or short range radar

? ADAS domain controller

? HVAC controller design

? Machine vision camera

? Rack server motherboard

? IP telephone

3 Description

The TXV0108-Q1 is a 8-bit, dual-supply direction

controlled low-skew, low-jitter voltage translation

device. This device can be used for redriving, voltage

translation and power isolation when implementing

skew sensitive interface, such as RGMII between

Ethernet MAC and PHY devices. The Ax I/O pins and

control pins (DIR, OE) are referenced to VCCA logic

levels, and Bx I/O pins are referenced to VCCB logic

levels. This device has improved channel-to-channel

skew, duty cycle distortion and symmetric rise and fall

time for applications requiring strict timing conditions.

This device is fully specified for partial-power-down

applications using Ioff. The Ioff circuitry disables the

outputs, thus preventing damaging current backflow

through the device when it is powered down.

The VCC isolation feature is designed so that if either

VCC supply is at or near 0 V both ports will switch to

a high-impedance state. This feature enables power

isolation for communications across multiple MACs

and PHYs, and is beneficial in situations where MACs

and PHYs are powered up asynchronously preventing

current backflow between devices.

A High on DIR allows data transmission from A to

B while a Low on DIR allows data transmission from

B to A when OE is set to Low. When OE is set to

High, both Ax and Bx pins will be forced into a highimpedance

state. See Device Functional Modes for a

summary of the operation of the control logic.