UPB1005K中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The μPB1005K is a silicon monolithic integrated circuit for GPS receiver. This IC is designed as double

conversion RF block integrated RF/IF down-converter + PLL frequency synthesizer on 1 chip.

The μPB1005K features 36-pin plastic QFN, fixed prescaler and supply voltage. The 36-pin plastic QFN package is suitable for high density surface mounting. The fixed division internal prescaler is needless to input serial counter data. Supply voltage is 3 V. Thus, the μPB1005K can make RF block fewer components and lower power consumption.

FEATURES

? Double conversion : fREFin= 16.368 MHz, f2ndIFout= 4.092 MHz

? Integrated RF block : RF/IF frequency down-converter + PLL frequency synthesizer

? High-density surface mountable : 36-pin plastic QFN (6.0 ×6.0 ×0.95 mm)

? Needless to input counter data : fixed division internal prescaler

? VCO side division : ÷200 (÷25, ÷8 serial prescaler)

? Reference division : ÷2

? Supply voltage : VCC= 2.7 to 3.3 V

? Low current consumption : ICC= 45.0 mA TYP.@VCC= 3.0 V

? Gain adjustable externally : Gain control voltage pin (control voltage up vs. gain down)

APPLICATION

? Consumer use GPS receiver of reference frequency 16.368 MHz, 2nd IF frequency 4.092 MHz