UPD4701AGT中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

? X, Y 2-axis incremental encoder counter

? Counter input (Schmitt-triggered input)

X axis: XA, XB 2-phase signal

4-multiplication count method used

Y axis: YA, YB 2-phase signal

? Counters: 12-bit binary up/down counters (2 sets, X & Y)

Reset value: 000H

? Count data output: 8-bit parallel latch output ′ 2 (including key input flag)

? On-chip 3-contact-point key input buffer circuit

? CMOS

? Single +5 V power supply