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UR5596-S08-T規(guī)格書詳情
DESCRIPTION
The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to provide excellent response to the load transients, and can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination.
FEATURES
* Source and sink current
* Low output voltage offset
* No external resistors required
* Linear topology
* Suspend To Ram (STR) functionality
* Low external component count
* Thermal shutdown protection
產(chǎn)品屬性
- 型號：
UR5596-S08-T
- 制造商：
UTC-IC
- 制造商全稱：
UTC-IC
- 功能描述：
DDR TERMINATION REGULATOR
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
97+ |
QFP |
1278 |
普通 |
詢價 | |||
只做原裝 |
24+ |
QFP |
36520 |
一級代理/放心采購 |
詢價 | ||
UTC |
20232024 |
SOT223 |
6000 |
老牌代理,長期現(xiàn)貨 |
詢價 | ||
NULL |
2447 |
QFP |
100500 |
一級代理專營品牌!原裝正品,優(yōu)勢現(xiàn)貨,長期排單到貨 |
詢價 | ||
UNK |
2022 |
QFP32 |
2300 |
原裝現(xiàn)貨,誠信經(jīng)營! |
詢價 |
