VSC8117QP2中文資料VITESSE數(shù)據(jù)手冊(cè)PDF規(guī)格書

General Description

The VSC8117 is an ATM/SONET/SDH compatible transceiver integrating an on-chip Clock Multiplication Unit (PLL) for the high speed clock as well as a clock and data recovery unit (CRU) with 8 bit serial-to-parallel and parallel-to-serial data conversion. The PLL clock is used for serialization in the transmit direction (Mux). The recovered clock is used for deserialization in the receive direction (Demux). The demultiplexer contains SONET/SDH frame detection and recovery. The device provides facility loopback, equipment loopback, and loop timing modes. The part is packaged in a 64-pin PQFP with integrated heat spreader for optimum thermal performance and reduced cost. The VSC8117 provides an integrated solution for ATM physical layers and SONET/SDH systems applications.

Features

? +3.3V/5V programmable PECL Serial Interface

? Provides Equipment, Facilities and Split

Loopback Modes as well as Loop Timing Mode

? Provides TTL and PECL reference clock inputs

? Meets Bellcore, ITU and ANSI Specifications for

Jitter Performance

? Low Power - 1.0 Watts Typical

? 64 PQFP Package

? Operates at Either STS-3/STM-1 (155.52Mb/s)

or STS-12/STM-4 (622.08Mb/s) Data Rates

? Compatible with Industry ATM UNI Devices

? On Chip Clock Generation of the 155.52MHz

or 622.08MHz High Speed Clock (Mux)

? On Chip Clock Recovery of the 155.52MHz or

622.08MHz High Speed Clock (Demux)

? 8 Bit Parallel TTL Interface

? SONET/SDH Frame Recovery

? Loss of Signal (LOS) Input & LOS Detection