W25P022AF-7中文資料華邦電子數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The W25P022A is a high-speed, low-power, synchronous-burst pipelined CMOS static RAM organized as 65,536 ′ 32 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both Pentium? burst mode and linear burst mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode reduces power dissipation.

FEATURES

? Synchronous operation

? High-speed access time: 6/7 nS (max.)

? Single +3.3V power supply

? Individual byte write capability

? 3.3V LVTTL compatible I/O

? Clock-controlled and registered input

? Asynchronous output enable

? Pipelined/non-pipelined data output capability

? Supports snooze mode (low-power state)

? Internal burst counter supports Intel burst mode & linear burst mode

? Supports both 2T/2T & 2T/1T mode

? Packaged in 100-pin QFP or TQFP