W9425G6DH中文資料華邦電子數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

W9425G6DH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 4,194,304 words × 4 banks × 16 bits. Using pipelined architecture and 0.11 μm process technology, W9425G6DH delivers a data bandwidth of up to 500M words per second (-4). To fully comply with the personal computer industrial standard, W9425G6DH is sorted into four speed grades: -4, -5, -6 and -75. The -4 is compliant to the DDR500/CL3 specification. The -5 is compliant to the DDR400/CL3 specification. The -6 is compliant to the DDR333/CL2.5 specification (the -6I grade which is guaranteed to support -40°C ~ 85°C). The -75 is compliant to the DDR266/CL2 specification (the 75I grade which is guaranteed to support -40°C ~ 85°C).

FEATURES

? 2.5V ±0.2V Power Supply for DDR266/DDR333

? 2.6V ±0.1V Power Supply for DDR400/DDR500

? Up to 250 MHz Clock Frequency

? Double Data Rate architecture; two data transfers per clock cycle

? Differential clock inputs (CLK and CLK )

? DQS is edge-aligned with data for Read; center-aligned with data for Write

? CAS Latency: 2, 2.5 and 3

? Burst Length: 2, 4 and 8

? Auto Refresh and Self Refresh

? Precharged Power Down and Active Power Down

? Write Data Mask

? Write Latency = 1

? 7.8μS refresh interval (8K / 64 mS refresh)

? Maximum burst refresh cycle: 8

? Interface: SSTL_2

? Packaged in TSOP II 66-pin, 400 mil, 0.65 mm pin pitch, using Pb free with RoHS compliant