WED2DL32512V40BC中文資料WEDC數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The WEDC SyncBurst - SRAM family employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 16Mb SyncBurst SRAMs integrate two 512K x 16 SRAMs into a single BGA package to provide 512K x 32 configuration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE), burst control input (ADSC) and byte write enables (BW0-3). Asynchronous inputs include the output enable (OE), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. Write cycles can be from one to four bytes wide, as controlled by the write control inputs. Burst operation can be initiated with the address status controller (ADSC) input.

FEATURES

■ Fast clock speed: 200, 166, 150 & 133MHz

■ Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns

■ Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns

■ Single +3.3V power supply (VDD)

■ Separate +3.3V or +2.5V isolated output buffer supply (VDDQ)

■ Snooze Mode for reduced-power standby

■ Single-cycle deselect

■ Common data inputs and data outputs

■ Individual Byte Write control and Global Write

■ Clock-controlled and registered addresses, data I/Os and control signals

■ Burst control (interleaved or linear burst)

■ Packaging:

? 119-bump BGA package

■ Low capacitive bus loading