WF512K32N-70H1C5A中文資料WEDC數據手冊PDF規(guī)格書

FEATURES

■ Access Times of 60, 70, 90, 120, 150ns

■ Packaging

? 66 pin, PGA Type, 1.075 square, Hermetic Ceramic HIP (Package 400(1)).

? 68 lead, 40mm, Low Capacitance Hermetic CQFP (Package 501)1

? 68 lead, 40mm, Low Profi le 3.5mm (0.140), CQFP (Package 502)1

? 68 lead, 22.4mm (0.880) Low Profi le CQFP (G2U) 3.5mm (0.140) high, (Package 510)1

? 68 lead, 22.4mm (0.880) CQFP (G2L) 5.08mm (0.200) high, Package (528)

■ 1,000,000 Erase/Program Cycles Minimum

■ Sector Architecture

? 8 equal size sectors of 64KBytes each

? Any combination of sectors can be concurrently erased. Also supports full chip erase

■ Organized as 512Kx32

■ Commercial, Industrial and Military Temperature Ranges

■ 5 Volt Programming. 5V ± 10 Supply.

■ Low Power CMOS, 6.5mA Standby

■ Embedded Erase and Program Algorithms

■ TTL Compatible Inputs and CMOS Outputs

■ Built-in Decoupling Caps for Low Noise Operation

■ Page Program Operation and Internal Program Control Time

■ Weight

WF512K32 - XG2UX5 - 8 grams typical

WF512K32N - XH1X5 - 13 grams typical

WF512K32 - XG4TX51 - 20 grams typical

WF512K32-XG2LX5 - 8 grams typical