74ALVC574PW集成電路（IC）的觸發(fā)器規(guī)格書PDF中文資料

1. General description

The 74ALVC574 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and

3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE)

are common to all flip-flops.

The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold

times requirements on the LOW to HIGH CP transition.

When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When pin OE is

HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect

the state of the flip-flops.

The 74ALVC574 is functionally identical to the 74ALVC374, but has a different pin arrangement.

2. Features and benefits

? Wide supply voltage range from 1.65 V to 3.6 V

? 3.6 V tolerant inputs/outputs

? CMOS low power consumption

? Direct interface with TTL levels (2.7 V to 3.6 V)

? Power-down mode

? Latch-up performance exceeds 250 mA

? Complies with JEDEC standards:

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8B (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114E exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V