79RC32H434400BCI中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Device Overview

The RC32434 is a member of the IDT? Interprise? family of PCI

integrated communications processors. It incorporates a high performance

CPU core and a number of on-chip peripherals. The integrated

processor is designed to transfer information from I/O modules to main

memory with minimal CPU intervention, using a highly sophisticated

direct memory access (DMA) engine. All data transfers through the

RC32434 are achieved by writing data from an on-chip I/O peripheral to

main memory and then out to another I/O module.

Features

32-bit CPU Core

– MIPS32 instruction set

– Cache Sizes: 8KB instruction and data caches, 4-Way set

associative, cache line locking, non-blocking prefetches

– 16 dual-entry JTLB with variable page sizes

– 3-entry instruction TLB

– 3-entry data TLB

– Max issue rate of one 32x16 multiply per clock

– Max issue rate of one 32x32 multiply every other clock

– CPU control with start, stop, and single stepping

– Software breakpoints support

– Hardware breakpoints on virtual addresses

– ICE Interface that is compatible with v2.5 of the EJTAG Specification