HEF4035BT中文資料飛利浦數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The HEF4035B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions (O0 to O3), a true/complement input (T/C) and an overriding asynchronous master reset input (MR). Each register is of a D-type master-slave flip-flop.

Operation is synchronous (except for MR) and is edge-triggered on the LOW to HIGH transition of the CP input. When PE is HIGH, data is loaded into the register from P0 to P3 on the LOW to HIGH transition of CP.

When PE is LOW, data is shifted into the first register position from J and K and all the data in the register is shifted one position to the right on the LOW to HIGH transition of CP. D-type entry is obtained by interconnecting J and K. When J = HIGH and K = LOW the first stage is in the toggle mode. When J = LOW and K = HIGH the first stage is in the hold mode.