首頁>P102-04SCL>規(guī)格書詳情

P102-04SCL中文資料PLL數(shù)據(jù)手冊PDF規(guī)格書

P102-04SCL
廠商型號(hào)

P102-04SCL

功能描述

Low Skew Output Buffer

文件大小

236.44 Kbytes

頁面數(shù)量

6

生產(chǎn)廠商 PhaseLink Corporation
企業(yè)簡稱

PLL

中文名稱

PhaseLink Corporation官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊

下載地址一下載地址二

更新時(shí)間

2025-5-25 13:02:00

人工找貨

P102-04SCL價(jià)格和庫存,歡迎聯(lián)系客服免費(fèi)人工找貨

P102-04SCL規(guī)格書詳情

DESCRIPTION

The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±350 ps, the device acts as a zero delay buffer.

FEATURES

? Frequency range 50 ~ 120MHz.

? Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).

? Zero input - output delay.

? Less than 700 ps device - device skew.

? Less than 250 ps skew between outputs.

? Less than 200 ps cycle - cycle jitter.

? Output Enable function tri-state outputs.

? 3.3V operation.

? Available in 8-Pin 150mil SOIC.

產(chǎn)品屬性

  • 型號(hào):

    P102-04SCL

  • 制造商:

    PLL

  • 制造商全稱:

    PLL

  • 功能描述:

    Low Skew Output Buffer

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫存 備注 價(jià)格
NXP
21+
689-TEPBGA II(31x31)
104
100%全新原裝 亞太地區(qū)XILINX、FREESCALE-NXP AD專業(yè)
詢價(jià)
PHASELINK
23+
SOP8
50000
全新原裝正品現(xiàn)貨,支持訂貨
詢價(jià)
SEMTECH
2025+
SOP-8
3565
全新原廠原裝產(chǎn)品、公司現(xiàn)貨銷售
詢價(jià)
SC
23+
SOP-8
56000
原廠授權(quán)一級(jí)代理,專業(yè)海外優(yōu)勢訂貨,價(jià)格優(yōu)勢、品種
詢價(jià)
ST
23+
TO-92
16900
正規(guī)渠道,只有原裝!
詢價(jià)
NXP(恩智浦)
2447
TEPBGAII-689(31x31)
31500
27個(gè)/托盤一級(jí)代理專營品牌!原裝正品,優(yōu)勢現(xiàn)貨,長
詢價(jià)
尼克森NIKOS
19+
()
880000
明嘉萊只做原裝正品現(xiàn)貨
詢價(jià)
SC
23+
SOP8
50000
全新原裝正品現(xiàn)貨,支持訂貨
詢價(jià)
ST
24+
TO-92
200000
原裝進(jìn)口正口,支持樣品
詢價(jià)
NXP
22+
689TEPBGA II (31x31)
9000
原廠渠道,現(xiàn)貨配單
詢價(jià)