PEF20570中文資料英飛凌數(shù)據(jù)手冊PDF規(guī)格書
PEF20570規(guī)格書詳情
Addendum to “DELIC Clock System Synchronization”
The DELIC Clock System Synchronization is described in the DELIC-LC PEB 20570/DELIC-PB PEB 20571 Data Sheet, independent of the version (2.1 .. 3.1).
As an addendum to chapter “DELIC Clock System Synchronization” of the DELICLC/DELIC-PB Data Sheet the following describes the system behaviour when using the VIP PEB 20590 or PEB 20591 in LT-T mode, for example when synchronizing to the Central Office.
When the Central Office is activated, its clock signal is retrieved by the RxPLL of the VIP and a 1.536 MHz reference signal is generated and used as input signal for the DELIC DCXO (pin XCLK). This signal is divided down to 8 kHz and used as input for the DCXO phase detector (PD). The second input to PD is another 8 kHz signal which originates from the 16.384 MHz output of the DCXO.
The DELIC PLL multiplies the 16.384 MHz DCXO signal up to 61.44 MHz. A divider generates the 15.36 MHz layer 1 clock which is used to clock the VIP.
產(chǎn)品屬性
- 型號：
PEF20570
- 制造商：
INFINEON
- 制造商全稱：
Infineon Technologies AG
- 功能描述：
DSP Embedded Line and Port Interface Controller
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
INTEL/英特爾 |
20+ |
SMD |
880000 |
明嘉萊只做原裝正品現(xiàn)貨 |
詢價 | ||
Infineon |
23+ |
QFP |
1007 |
專業(yè)優(yōu)勢供應(yīng) |
詢價 | ||
INF |
23+ |
QFP |
4500 |
全新原裝、誠信經(jīng)營、公司現(xiàn)貨銷售! |
詢價 | ||
Infineo |
1733+ |
QFP100 |
6528 |
只做進(jìn)口原裝正品假一賠十! |
詢價 | ||
INF |
23+ |
QFP |
3600 |
絕對全新原裝!現(xiàn)貨!特價!請放心訂購! |
詢價 | ||
INFINEON/英飛凌 |
QFP |
98900 |
原廠集團(tuán)化配單-有更多數(shù)量-免費(fèi)送樣-原包裝正品現(xiàn)貨- |
詢價 | |||
Infineon(英飛凌) |
23+ |
7350 |
現(xiàn)貨供應(yīng),當(dāng)天可交貨!免費(fèi)送樣,原廠技術(shù)支持!!! |
詢價 | |||
24+ |
3000 |
公司存貨 |
詢價 | ||||
INFINEON/英飛凌 |
23+ |
QFP |
98900 |
原廠原裝正品現(xiàn)貨!! |
詢價 | ||
英飛凌 |
22+ |
NA |
500000 |
萬三科技,秉承原裝,購芯無憂 |
詢價 |
