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74ALVC74D集成電路（IC）的觸發(fā)器規(guī)格書PDF中文資料

廠商型號	74ALVC74D
參數(shù)屬性	74ALVC74D 封裝/外殼為14-SOIC（0.154"，3.90mm 寬）；包裝為卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶；類別為集成電路（IC）的觸發(fā)器；產(chǎn)品描述：IC FF D-TYPE DUAL 1BIT 14SO
功能描述	Dual D-type flip-flop with set and reset; positive-edge trigger
封裝外殼	14-SOIC（0.154"，3.90mm 寬）
文件大小	258.67 Kbytes
頁面數(shù)量	16 頁
生產(chǎn)廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-2-22 22:59:00
人工找貨	74ALVC74D價格和庫存，歡迎聯(lián)系客服免費人工找貨

1. General description

The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs,

clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.

The set and reset are asynchronous active LOW inputs that operate independently of the clock

input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition

of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock

transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly

tolerant to slower clock rise and fall times.

2. Features and benefits

? Wide supply voltage range from 1.65 V to 3.6 V

? Complies with JEDEC standard:

? JESD8-7 (1.65 to 1.95 V)

? JESD8-5 (2.3 to 2.7 V)

? JESD8B (2.7 to 3.6 V)

? 3.6 V tolerant inputs/outputs

? CMOS low power consumption

? Direct interface with TTL levels (2.7 V to 3.6 V)

? Power-down mode

? Latch-up performance exceeds 250 mA

? ESD protection:

? HBM JESD22-A114E exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Specified from -40 °C to +85 °C