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PLL102-10SC-R中文資料PLL數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
PLL102-10SC-R規(guī)格書(shū)詳情
DESCRIPTION
The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±350 ps, the device acts as a zero delay buffer.
FEATURES
? Frequency range 50 ~ 120MHz.
? Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs.
? Zero input - output delay.
? Less than 700 ps device - device skew.
? Less than 250 ps skew between outputs.
? Less than 100 ps cycle - cycle jitter.
? 2.5V or 3.3V power supply operation.
? Available in 8-Pin SOIC or MSOP package.
產(chǎn)品屬性
- 型號(hào)：
PLL102-10SC-R
- 制造商：
PLL
- 制造商全稱(chēng)：
PLL
- 功能描述：
Low Skew Output Buffer
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
PHASELINK |
22+23+ |
SSOP |
36452 |
絕對(duì)原裝正品全新進(jìn)口深圳現(xiàn)貨 |
詢(xún)價(jià) | ||
16+ |
FBGA |
4000 |
進(jìn)口原裝現(xiàn)貨/價(jià)格優(yōu)勢(shì)! |
詢(xún)價(jià) | |||
PHASELIN |
23+ |
NA/ |
30 |
優(yōu)勢(shì)代理渠道,原裝正品,可全系列訂貨開(kāi)增值稅票 |
詢(xún)價(jià) | ||
PHASELIN |
SSOP48 |
899933 |
集團(tuán)化配單-有更多數(shù)量-免費(fèi)送樣-原包裝正品現(xiàn)貨-正規(guī) |
詢(xún)價(jià) | |||
24+ |
SSOP |
2700 |
全新原裝自家現(xiàn)貨優(yōu)勢(shì)! |
詢(xún)價(jià) | |||
PHASELIN |
22+ |
SSOP48 |
5000 |
全新原裝現(xiàn)貨!自家?guī)齑? |
詢(xún)價(jià) | ||
PHASELIN |
589220 |
16余年資質(zhì) 絕對(duì)原盒原盤(pán) 更多數(shù)量 |
詢(xún)價(jià) | ||||
PHASELIN |
0350+ |
SSOP48 |
30 |
普通 |
詢(xún)價(jià) | ||
PHASELINK |
23+ |
SSOP |
89630 |
當(dāng)天發(fā)貨全新原裝現(xiàn)貨 |
詢(xún)價(jià) | ||
24+ |
SSOP |
17 |
詢(xún)價(jià) |
